In integrated circuits, an interface is used for testing the circuit. Conventionally, the integrated circuits incorporate a JTAG (Joint Test Action Group) test logic interface. The JTAG test logic interface is the IEEE standard 1149.1 compatible device. The IEEE standard 1149.1 compatible device includes an interface having five ports, two ports for control, one port each for an input serial test data and an output serial test data, and an optional fifth port for providing an asynchronous initialization of the test logic. The standard allows test instructions and data to be serially stored into the integrated circuits and enables the subsequent test results to be serially read out.
FIG. 1 illustrates a conventional JTAG test interface architecture. The architecture includes an instruction decoder 126, an instruction register 128, a TAP controller 130, a plurality of test data registers and a test access port TAP. The test access port TAP can provide access to numerous test features built into a component. The architecture is complied with the IEEE standard 1149.1. The plurality of test data registers includes a boundary scan register 118, a bypass register 116 and optional user data registers such as data register 120 and data register 122. The operation and use of the JTAG test interface requires four input connections such as TCK (Test Clock), TDI (Test Data In), TMS (Test Mode Select) and TRST (Test Reset) bar, of the test access port which play a vital role in deciding a testing time for the integrated circuit.
Thus, each hardware pin takes up a physical space on the integrated circuit and the circuit board where the integrated circuit is located. Therefore, the cost associated with the manufacturing of the integrated circuits and circuit boards increases with the increase in the number of hardware pins.
Another approach that has been used for reducing the number of hardware pins is to allow alternate functions to be mapped onto input pins. But this limits a user to stick to a specific functionality at one time. Thus, imposes a problem for the integrated circuits having the low pin count.
Therefore, there is a need for an architecture which requires lesser number of hardware pins so that a greater number of units can be tested in parallel during production time to increase the throughput, and hence reduce the cost of the unit, reduce time to market and increase profit.